Strimy a dit:

Je n‘ai toujours pas compris de quel manière l’ECC sera différent en DDR5.

Je n‘ai pas trouvé beaucoup de ressource précise sur ce point, sinon cette doc de Micron, avec ce passage :

On-Die Error Correction Code (ECC)
RAS improvements like on-die ECC reduce the system error correction burden by performing correction during READ commands prior to outputting the data from the DDR5 device. DDR5 SDRAM ECC is implemented as single error correction (SEC), pairing 128 data bits with 8 parity bits to form a 136-bit codeword that is stored in the DRAM during a WRITE command. During subsequent READ commands to that address, a syndrome will be calculated based on the 136 bits, correcting any single-bit errors that may occur.
DDR5 designs implement the ECC with Hamming codes, where data bits are arranged into quadrants to align with system-level error correction coverage. Since 8 parity bits with 128 data bits do not allow for double-bit detection, the Hamming codes will "alias" a syndrome bit for two error bits within a pair of quadrants, into the other quadrants or into an "unused" data bit. This means that two error bits within quadrants 1 and/or 2 will alias to quadrant 3 or 4, or to an unused data bit. Likewise, two error bits within quadrants 3 and/or 4 will alias to quadrants 1 or 2, or to an unused data bit. This
allows the errors to still appear as a double bit fail to the system-level error correction.
An additional feature of the DDR5 SDRAM ECC is the error check and scrub (ECS) function. The ECS function is a read of internal data and the writing back of corrected data if an error occurred. ECS can be used as a manual function initiated by a Multi-Purpose Command (MPC), or the DDR5 SDRAM can run the ECS in automatic mode, where the DRAM schedules and performs the ECS commands as needed to complete a full scrub of the data bits in the array within the recommended 24-hour period. At the completion of a full-array scrub, the DDR5 reports the number of errors that were corrected during the scrub (once the error count exceeds a minimum fail threshold) and reports the row with the highest number of errors, which is also subject to a minimum threshold.

ashlol a dit:

Ba j‘ai 55Go/s de bande passante sur ma ram DDR4 OC à 3800 donc oui 6.4 Go/s c’est ridicule ou j‘ai pas compris un truc.

Tu confonds effectivement différentes choses. Pour faire simple, le 6400 Mb/s annoncé pour la DDR5 à terme est à comparer avec le 3800 que tu mentionnes dans ton cas.